Invention Grant
- Patent Title: Integrated circuits and methods for forming integrated circuits
-
Application No.: US16221815Application Date: 2018-12-17
-
Publication No.: US11018075B2Publication Date: 2021-05-25
- Inventor: Carl Naylor , Ashish Agrawal , Kevin Lin , Abhishek Sharma , Mauro Kobrinsky , Christopher Jezewski , Urusa Alaan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: 2SPL Patent Attorneys PartG mbB
- Agent Kieran O'Leary
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L23/40 ; H01L21/822 ; H01L23/532 ; H01L21/70

Abstract:
An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
Public/Granted literature
- US11164809B2 Integrated circuits and methods for forming integrated circuits Public/Granted day:2021-11-02
Information query
IPC分类: