- 专利标题: Techniques for enhancing vertical gate-all-around FET performance
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申请号: US16560679申请日: 2019-09-04
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公开(公告)号: US11069686B2公开(公告)日: 2021-07-20
- 发明人: Injo Ok , Choonghyun Lee , Soon-Cheon Seo , Seyoung Kim
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Michael J. Chang, LLC
- 代理商 Randall Bluestone
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L29/78 ; H01L29/51 ; H01L21/8238 ; H01L29/66 ; H01L29/40 ; H01L29/786
摘要:
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
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