Invention Grant
- Patent Title: Prefetching write permissions into address translation cache
-
Application No.: US16361512Application Date: 2019-03-22
-
Publication No.: US11126554B2Publication Date: 2021-09-21
- Inventor: Rupin H. Vakharwala , Paula Petrica
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0862 ; G06F13/42 ; G06F12/1036

Abstract:
Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.
Public/Granted literature
- US20190220413A1 PREFETCHING WRITE PERMISSIONS INTO ADDRESS TRANSLATION CACHE Public/Granted day:2019-07-18
Information query