发明授权
- 专利标题: Conductive via and metal line end fabrication and structures resulting therefrom
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申请号: US16637930申请日: 2017-09-30
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公开(公告)号: US11145541B2公开(公告)日: 2021-10-12
- 发明人: Charles H. Wallace , Reken Patel , Hyunsoo Park , Mohit K. Haran , Debashish Basu , Curtis W. Ward , Ruth A. Brain
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2017/054641 WO 20170930
- 国际公布: WO2019/066978 WO 20190404
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L21/311 ; H01L23/522
摘要:
Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.
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