公开(公告)号：US11854787B2

公开(公告)日：2023-12-26

申请号：US17735006

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US10460993B2

公开(公告)日：2019-10-29

申请号：US15859327

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L29/417 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US10777656B2

公开(公告)日：2020-09-15

申请号：US16577993

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US09893167B2

公开(公告)日：2018-02-13

申请号：US15118838

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Kelin J. Kuhn ,  Curtis W. Ward

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/764 ,  H01L29/786

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US11063133B2

公开(公告)日：2021-07-13

申请号：US16925573

申请日：2020-07-10

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US10892223B2

公开(公告)日：2021-01-12

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US12218052B2

公开(公告)日：2025-02-04

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US12016170B2

公开(公告)日：2024-06-18

申请号：US18124936

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H10B10/00 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H10B10/15 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/66545 ,  H10B10/125

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US11646359B2

公开(公告)日：2023-05-09

申请号：US17233063

申请日：2021-04-16

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Curtis W. Ward ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.