Invention Grant
- Patent Title: System to reduce coolant use in an array of circuit boards
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Application No.: US15960127Application Date: 2018-04-23
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Publication No.: US11184997B2Publication Date: 2021-11-23
- Inventor: Joseph Andrew Broderick , Barrett M. Faneuf , Eric D. McAfee , Juan G. Cevallos , Jaime A. Sanchez , Emery E. Frey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H05K7/20
- IPC: H05K7/20 ; H05K7/14 ; H05K1/02 ; H05K7/02

Abstract:
Embodiments described herein may include apparatuses, systems and/or processes to encapsulate a circuit board to be cooled with a liquid coolant, that includes a first part dimensioned to receive the circuit board coupled with one or more heat sinks; a second part dimensioned to mate with the first part, and with a portion of a side of the circuit board around the one or more heat sinks to create a volume surrounding the circuit board, with a portion of the one or more heat sinks are outside the volume and is to be exposed to the liquid coolant, and a sealer to seal areas where the second part mates with the first part and the portion of the side of the circuit board, to prevent the liquid coolant from entering the volume. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20190045661A1 SYSTEM TO REDUCE COOLANT USE IN AN ARRAY OF CIRCUIT BOARDS Public/Granted day:2019-02-07
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