Invention Grant
- Patent Title: Semiconductor package, package on package structure and method of froming package on package structure
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Application No.: US15660968Application Date: 2017-07-27
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Publication No.: US11201142B2Publication Date: 2021-12-14
- Inventor: Li-Hsien Huang , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hua-Wei Tseng , Ming-Chih Yew , Yi-Jen Lai , Ming-Shih Yeh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/00 ; H01L23/544 ; H01L25/00 ; H01L21/56 ; H01L21/48 ; H01L25/065 ; H01L21/683 ; H01L23/31 ; H01L23/50 ; H01L23/538 ; H01L23/498

Abstract:
A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.
Public/Granted literature
- US20190035772A1 SEMICONDCUTOR PACKAGE, PACKAGE ON PACKAGE STRUCTURE AND METHOD OF FROMING PACKAGE ON PACKAGE STRUCTURE Public/Granted day:2019-01-31
Information query
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