公开(公告)号：US11257797B2

公开(公告)日：2022-02-22

申请号：US16689101

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/538 ,  H01L25/065

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US20220399325A1

公开(公告)日：2022-12-15

申请号：US17874492

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jen Lai ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Chen-Shien Chen ,  Kuo-Chio Liu

IPC: H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L21/56 ,  H01L23/60 ,  H01L23/00

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

公开(公告)号：US11145613B2

公开(公告)日：2021-10-12

申请号：US16124337

申请日：2018-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

IPC: H01L23/00

Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall.

公开(公告)号：US20190131264A1

公开(公告)日：2019-05-02

申请号：US16219453

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

IPC: H01L23/00

Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

公开(公告)号：US20190035772A1

公开(公告)日：2019-01-31

申请号：US15660968

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Ming-Chih Yew ,  Yi-Jen Lai ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

公开(公告)号：US10163843B2

公开(公告)日：2018-12-25

申请号：US15795547

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

IPC: H01L23/00

Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

公开(公告)号：US09735123B2

公开(公告)日：2017-08-15

申请号：US14209118

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo Lee ,  Yi-Chen Liu ,  Yung-Sheng Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11821 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13693 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01079 ,  H01L2224/1182 ,  H01L2924/00012 ,  H01L2924/04953 ,  H01L2924/01047

Abstract: A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.

公开(公告)号：US11201142B2

公开(公告)日：2021-12-14

申请号：US15660968

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Ming-Chih Yew ,  Yi-Jen Lai ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

公开(公告)号：US20200091122A1

公开(公告)日：2020-03-19

申请号：US16689101

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/538 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US20180068967A1

公开(公告)日：2018-03-08

申请号：US15795547

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05013 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00014

Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.