公开(公告)号：US20200043855A1

公开(公告)日：2020-02-06

申请号：US16365611

申请日：2019-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chung Lu ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Yueh-Ting Lin ,  Ming-Shih Yeh

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor device and the manufacturing method thereof are provided. The semiconductor device includes a package structure, a first die, a first containment structure, a pre-fill layer, and a plurality of conductive terminals. The package structure includes an attach zone, a keep-out zone around the attach zone. The first die is disposed on the package structure in the attach zone and electrically connected to the package structure. The first containment structure is disposed within the keep-out zone of the package structure and surrounds the first die. The pre-fill layer is disposed between the package structure and the first die and between the first containment structure and the first die, where the pre-fill layer is constrained within the first containment structure. The conductive terminals are disposed on the package structure, distributed around the keep-out zone of the package structure, and electrically connected to the package structure.

公开(公告)号：US10163803B1

公开(公告)日：2018-12-25

申请号：US15627449

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming-Shih Yeh

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.

公开(公告)号：US20250062136A1

公开(公告)日：2025-02-20

申请号：US18513957

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Ming-Shih Yeh

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

公开(公告)号：US11145633B2

公开(公告)日：2021-10-12

申请号：US16795523

申请日：2020-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

公开(公告)号：US11075150B2

公开(公告)日：2021-07-27

申请号：US16056532

申请日：2018-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Chiang Lin ,  Ming-Shih Yeh

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L21/48

Abstract: A redistribution structure includes a first dielectric layer and a first redistribution circuit layer. The first dielectric layer includes a first via opening. The first redistribution circuit layer is disposed on the first dielectric layer and includes a via portion filling the first via opening and a circuit portion connecting the via portion and extending over the first dielectric layer. A maximum vertical distance between an upper surface of the via portion and an upper surface of the circuit portion is substantially equal to or smaller than 0.5 μm.

公开(公告)号：US20190355687A1

公开(公告)日：2019-11-21

申请号：US15980662

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Yueh-Ting Lin ,  Ming-Shih Yeh

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/58

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.

公开(公告)号：US11450612B2

公开(公告)日：2022-09-20

申请号：US16924201

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  An-Jhih Su ,  Der-Chyang Yeh ,  Shih-Guo Shen ,  Chia-Nan Yuan ,  Ming-Shih Yeh

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

公开(公告)号：US11217570B2

公开(公告)日：2022-01-04

申请号：US16857161

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US11201142B2

公开(公告)日：2021-12-14

申请号：US15660968

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Ming-Chih Yew ,  Yi-Jen Lai ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

公开(公告)号：US20200006219A1

公开(公告)日：2020-01-02

申请号：US16258672

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming-Shih Yeh

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31 ,  H01L21/56 ,  H01L21/822 ,  H01L25/10 ,  H01L25/00

Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.