公开(公告)号：US20230402402A1

公开(公告)日：2023-12-14

申请号：US17663683

申请日：2022-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chien Hung Chen ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L21/563

Abstract: A semiconductor package including a recessed stiffener ring and a method of forming are provided. The semiconductor package may include a substrate, a semiconductor die bonded to the substrate, an underfill between the semiconductor die and the substrate, and a stiffener ring attached to the substrate, wherein the stiffener ring encircles the semiconductor die in a top view. The stiffener ring may include a recess that faces the semiconductor die.

公开(公告)号：US20230335477A1

公开(公告)日：2023-10-19

申请号：US18340387

申请日：2023-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81815

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US20230317661A1

公开(公告)日：2023-10-05

申请号：US18327252

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yen Lee ,  Chia-Kuei Hsu ,  Shang-Lun Tsai ,  Ming-Chih Yew ,  Po-Yao Lin

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/02311 ,  H01L2225/06517 ,  H01L2224/02381 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/0235 ,  H01L2224/1411 ,  H01L2224/02331

Abstract: A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

公开(公告)号：US11749644B2

公开(公告)日：2023-09-05

申请号：US17652764

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L23/3128

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US20230253303A1

公开(公告)日：2023-08-10

申请号：US18302500

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L25/18 ,  H01L23/49816 ,  H01L23/5383

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

公开(公告)号：US20230223364A1

公开(公告)日：2023-07-13

申请号：US18186348

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/538 ,  H01Q21/06 ,  H01Q9/28 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L23/49822 ,  H01L23/5383 ,  H01Q21/062 ,  H01Q21/065 ,  H01Q9/285 ,  H01Q9/045 ,  H01L2224/16227 ,  H01L24/16

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US20220344174A1

公开(公告)日：2022-10-27

申请号：US17346972

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

公开(公告)号：US11329006B2

公开(公告)日：2022-05-10

申请号：US16900815

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/00 ,  H01L23/36 ,  H01L23/40 ,  H01L23/31

Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.

公开(公告)号：US11270953B2

公开(公告)日：2022-03-08

申请号：US16284630

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng ,  Shuo-Mao Chen ,  Ming-Chih Yew

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H05K1/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

公开(公告)号：US09748156B1

公开(公告)日：2017-08-29

申请号：US15180264

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Shen Yeh ,  Cheng-Lin Huang ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Wen-Yi Lin ,  Ming-Chih Yew ,  Yu-Huan Chen ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/18 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/18 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.