Invention Grant
- Patent Title: Power MOS device with low gate charge and a method for manufacturing the same
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Application No.: US17005354Application Date: 2020-08-28
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Publication No.: US11211486B2Publication Date: 2021-12-28
- Inventor: Ming Qiao , Zhengkang Wang , Shida Dong , Bo Zhang
- Applicant: University of Electronic Science and Technology of China
- Applicant Address: CN Chengdu
- Assignee: University of Electronic Science and Technology of China
- Current Assignee: University of Electronic Science and Technology of China
- Current Assignee Address: CN Chengdu
- Agency: Bayramoglu Law Offices LLC
- Priority: CN202010352084.0 20200428
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/82 ; H01L29/423 ; H01L29/66 ; H01L21/8234
Abstract:
A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.
Public/Granted literature
- US20210336052A1 POWER MOS DEVICE WITH LOW GATE CHARGE AND A METHOD FOR MANUFACTURING THE SAME Public/Granted day:2021-10-28
Information query
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