公开(公告)号：US10720524B1

公开(公告)日：2020-07-21

申请号：US16536333

申请日：2019-08-09

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhengkang Wang ,  Dong Fang ,  Ruidi Wang ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.

公开(公告)号：US10510747B1

公开(公告)日：2019-12-17

申请号：US16140572

申请日：2018-09-25

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Chunlan Lai ,  Linrong He ,  Li Ye ,  Bo Zhang

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/324

Abstract: A BCD semiconductor device includes devices integrated on a single chip. The devices include a first high voltage nLIGBT device, a second high voltage nLIGBT device, a first high voltage nLDMOS device, a second high voltage nLDMOS device, a third high voltage nLDMOS device, a first high voltage pLDMOS device and low voltage NMOS, PMOS and PNP devices, and a diode device. A dielectric isolation is applied to the high voltage nLIGBT, nLDMOS and pLDMOS devices to realize a complete isolation between the high and low voltage devices. The nLIGBT, nLDMOS, NPN and low voltage NMOS and PMOS are integrated on the substrate of a single chip. The isolation region composed of the dielectric, the second conductivity type buried layer, the dielectric trench, and the first conductivity type implanted region realizes full dielectric isolation of high and low voltage devices. The six types of high voltage transistors have multiple channels.

公开(公告)号：US11855203B2

公开(公告)日：2023-12-26

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Liu Yuan ,  Zhao Wang ,  Wenliang Liu ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

公开(公告)号：US10608106B2

公开(公告)日：2020-03-31

申请号：US15955706

申请日：2018-04-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhengkang Wang ,  Ruidi Wang ,  Zhao Qi ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.

公开(公告)号：US11222890B2

公开(公告)日：2022-01-11

申请号：US16839089

申请日：2020-04-03

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Linrong He ,  Yi Li ,  Chunlan Lai ,  Bo Zhang

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

公开(公告)号：US11888022B2

公开(公告)日：2024-01-30

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong Zhang ,  Ning Tang ,  Ke Zhang ,  Nailong He ,  Ming Qiao ,  Zhaoji Li ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L29/407 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7823 ,  H01L29/7824

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

公开(公告)号：US11424331B1

公开(公告)日：2022-08-23

申请号：US17348790

申请日：2021-06-16

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Dingxiang Ma ,  Zhengkang Wang ,  Bo Zhang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.

公开(公告)号：US11211486B2

公开(公告)日：2021-12-28

申请号：US17005354

申请日：2020-08-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhengkang Wang ,  Shida Dong ,  Bo Zhang

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.

公开(公告)号：US10910362B2

公开(公告)日：2021-02-02

申请号：US16017978

申请日：2018-06-25

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhao Qi ,  Jiamu Xiao ,  Longfei Liang ,  Danye Liang ,  Bo Zhang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

公开(公告)号：US12027577B2

公开(公告)日：2024-07-02

申请号：US17351267

申请日：2021-06-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Shuhao Zhang ,  Zhangyi'an Yuan ,  Dican Hou ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0878 ,  H01L29/66681 ,  H01L29/7816

Abstract: A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.