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公开(公告)号:US10068965B1
公开(公告)日:2018-09-04
申请号:US15718001
申请日:2017-09-28
Inventor: Ming Qiao , Yang Yu , Wentong Zhang , Zhengkang Wang , Zhenya Zhan , Bo Zhang
IPC: H01L29/06 , H01L29/78 , H01L27/02 , H01L29/40 , H01L29/739 , H01L29/735
Abstract: The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different doping types alternating mode is provided at least below, on a left side of, or on a right side of the dielectric trench region. The device also includes a dielectric layer, a body field plate, a polysilicon gate, a gate oxide layer, a first N-type heavy doping region, a second N-type heavy doping region, a P-type heavy doping region, a P-well region, the first N-type doping pillar, the second N-type doping pillar, the third N-type doping pillar, the first P-type doping pillar, and the second P-type doping pillar. The invention adopts a dielectric trench region in the drift region to keep the breakdown voltage BV of the device while reducing the surface area of the device, and effectively reducing the device's specific On-Resistance RON,sp.
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公开(公告)号:US10720524B1
公开(公告)日:2020-07-21
申请号:US16536333
申请日:2019-08-09
Inventor: Ming Qiao , Zhengkang Wang , Dong Fang , Ruidi Wang , Bo Zhang
IPC: H01L29/78 , H01L29/40 , H01L29/423 , H01L29/66
Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.
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公开(公告)号:US10608106B2
公开(公告)日:2020-03-31
申请号:US15955706
申请日:2018-04-18
Inventor: Ming Qiao , Zhengkang Wang , Ruidi Wang , Zhao Qi , Bo Zhang
Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.
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公开(公告)号:US11424331B1
公开(公告)日:2022-08-23
申请号:US17348790
申请日:2021-06-16
Inventor: Ming Qiao , Dingxiang Ma , Zhengkang Wang , Bo Zhang
Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.
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公开(公告)号:US11211486B2
公开(公告)日:2021-12-28
申请号:US17005354
申请日:2020-08-28
Inventor: Ming Qiao , Zhengkang Wang , Shida Dong , Bo Zhang
IPC: H01L29/78 , H01L21/82 , H01L29/423 , H01L29/66 , H01L21/8234
Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.
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