Invention Grant
- Patent Title: Package structure and manufacturing method thereof
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Application No.: US16857161Application Date: 2020-04-23
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Publication No.: US11217570B2Publication Date: 2022-01-04
- Inventor: Wei-Yu Chen , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Li-Hsien Huang , Po-Hao Tsai , Ming-Shih Yeh , Ta-Wei Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/48 ; H01L23/00 ; H01L23/31 ; H01L25/00 ; H01L21/56 ; H01L21/683 ; H01L23/538 ; H01L21/768 ; H01L25/065

Abstract:
A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
Public/Granted literature
- US20200251456A1 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-08-06
Information query
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