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公开(公告)号:US20240363457A1
公开(公告)日:2024-10-31
申请号:US18767481
申请日:2024-07-09
发明人: Kuan-Hung Chen , Hong-Seng Shue , Po-Hao Tsai , Mirng-Ji Lii
IPC分类号: H01L23/10 , H01L21/50 , H01L21/762 , H01L23/522
CPC分类号: H01L23/10 , H01L21/50 , H01L21/76297 , H01L23/5226
摘要: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.
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公开(公告)号:US12087648B2
公开(公告)日:2024-09-10
申请号:US17659048
申请日:2022-04-13
发明人: Kuan-Hung Chen , Hong-Seng Shue , Po-Hao Tsai , Mirng-Ji Lii
IPC分类号: H01L23/10 , H01L21/50 , H01L21/762 , H01L23/522
CPC分类号: H01L23/10 , H01L21/50 , H01L21/76297 , H01L23/5226
摘要: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.
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公开(公告)号:US20240250019A1
公开(公告)日:2024-07-25
申请号:US18598266
申请日:2024-03-07
发明人: Ting-Li Yang , Po-Hao Tsai , Ming-Da Cheng , Yung-Han Chuang , Hsueh-Sheng Wang
IPC分类号: H01L23/522 , H01L21/48 , H01L23/00 , H01L23/528
CPC分类号: H01L23/5226 , H01L21/486 , H01L23/528 , H01L24/11 , H01L24/14
摘要: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.
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公开(公告)号:US11996372B2
公开(公告)日:2024-05-28
申请号:US17372677
申请日:2021-07-12
发明人: Po-Yao Chuang , Po-Hao Tsai , Shin-Puu Jeng
IPC分类号: H01L23/66 , H01L21/48 , H01L21/56 , H01L23/367 , H01L23/498 , H01L25/065 , H01Q1/22
CPC分类号: H01L23/66 , H01L21/4857 , H01L21/568 , H01L23/367 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L25/0655 , H01Q1/2283 , H01L2223/6677
摘要: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.
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公开(公告)号:US11901302B2
公开(公告)日:2024-02-13
申请号:US17360313
申请日:2021-06-28
发明人: Jing-Cheng Lin , Chen-Hua Yu , Po-Hao Tsai
IPC分类号: H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L25/00 , H01L25/065 , H01L21/48 , H01L21/56 , H01L21/683
CPC分类号: H01L23/5389 , H01L21/486 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L23/3128 , H01L2221/68345 , H01L2221/68359 , H01L2221/68372 , H01L2224/18 , H01L2224/214 , H01L2224/2919 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2224/18 , H01L2924/0001 , H01L2224/2919 , H01L2924/00014
摘要: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
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公开(公告)号:US11862588B2
公开(公告)日:2024-01-02
申请号:US17323506
申请日:2021-05-18
发明人: Chen-Shien Chen , Ting-Li Yang , Po-Hao Tsai , Chien-Chen Li , Ming-Da Cheng
CPC分类号: H01L24/05 , H01L23/3171 , H01L24/03 , H01L24/16 , H01L2224/0236 , H01L2224/02311 , H01L2224/02313 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/16225
摘要: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.
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公开(公告)号:US11855059B2
公开(公告)日:2023-12-26
申请号:US17808621
申请日:2022-06-24
发明人: Po-Hao Tsai , Techi Wong , Po-Yao Chuang , Shin-Puu Jeng , Meng-Wei Chou , Meng-Liang Lin
CPC分类号: H01L25/18 , H01L21/566 , H01L23/3114 , H01L23/3128 , H01L24/09 , H01L24/17 , H01L24/32 , H01L24/73 , H01L2224/0231 , H01L2224/02379 , H01L2224/0401
摘要: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
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公开(公告)号:US11824007B2
公开(公告)日:2023-11-21
申请号:US17690206
申请日:2022-03-09
发明人: Po-Hao Tsai , Po-Yao Chuang , Meng-Liang Lin , Yi-Wen Wu , Shin-Puu Jeng , Techi Wong
IPC分类号: H01L23/538 , H01L21/48 , H01L21/56 , H01L21/768 , H01L23/00
CPC分类号: H01L23/5384 , H01L21/4885 , H01L21/56 , H01L21/76802 , H01L23/5385 , H01L23/5386 , H01L24/14
摘要: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
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公开(公告)号:US11776935B2
公开(公告)日:2023-10-03
申请号:US17853524
申请日:2022-06-29
发明人: Jing-Cheng Lin , Chen-Hua Yu , Po-Hao Tsai
IPC分类号: H01L25/065 , H01L23/50 , H01L23/552 , H01L21/3205 , H01L25/00 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/31 , H01L21/56
CPC分类号: H01L25/0657 , H01L21/3205 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L25/50 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06548 , H01L2924/15311 , H01L2924/181 , H01L2924/181 , H01L2924/00012 , H01L2224/48091 , H01L2924/00014
摘要: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
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公开(公告)号:US11682599B2
公开(公告)日:2023-06-20
申请号:US16199535
申请日:2018-11-26
发明人: Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号: H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L23/538
CPC分类号: H01L23/3114 , H01L21/4857 , H01L21/563 , H01L23/3128 , H01L23/49822 , H01L23/5389
摘要: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.
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