Invention Grant
- Patent Title: Method for manufacturing reformed sic wafer, epitaxial layer-attached sic wafer, method for manufacturing same, and surface treatment method
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Application No.: US16495282Application Date: 2018-03-20
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Publication No.: US11261539B2Publication Date: 2022-03-01
- Inventor: Satoshi Torimi , Yusuke Sudo , Masato Shinohara , Youji Teramoto , Takuya Sakaguchi , Satoru Nogami , Makoto Kitabatake
- Applicant: Toyo Tanso Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: Toyo Tanso Co., Ltd.
- Current Assignee: Toyo Tanso Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Westerman, Hattori, Daniels and Adrian, LLP
- Priority: JPJP2017-055240 20170322,JPJP2017-210585 20171031
- International Application: PCT/JP2018/011221 WO 20180320
- International Announcement: WO2018/174105 WO 20180927
- Main IPC: H01L21/02
- IPC: H01L21/02 ; C30B25/18 ; C30B29/36 ; H01L29/34 ; H01L29/16 ; C30B25/20

Abstract:
In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.
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