- 专利标题： Compound instruction set architecture for a neural inference chip
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申请号： US16202871申请日： 2018-11-28
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公开(公告)号： US11263011B2公开(公告)日： 2022-03-01
- 发明人: Andrew S. Cassidy , Rathinakumar Appuswamy , John V. Arthur , Pallab Datta , Michael V. Debole , Steven K. Esser , Myron D. Flickner , Dharmendra S. Modha , Hartmut Penner , Jun Sawada , Brian Taba
- 申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 代理机构： Foley Hoag, LLP
- 代理商 Erik A. Huestis; Stephen J. Kenny
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06N3/02 ; G06F9/32
摘要：
A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register.