Invention Grant
- Patent Title: Semiconductor fabrication method for producing nano-scaled electrically conductive lines
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Application No.: US17081337Application Date: 2020-10-27
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Publication No.: US11264271B2Publication Date: 2022-03-01
- Inventor: Martin O'Toole , Zsolt Tokei , Christopher Wilson , Stefan Decoster
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP19217971 20191219
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/033 ; H01L23/538

Abstract:
A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.
Public/Granted literature
- US20210193512A1 Semiconductor Fabrication Method for Producing Nano-Scaled Electrically Conductive Lines Public/Granted day:2021-06-24
Information query
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