Invention Grant
- Patent Title: Thin film transistors with spacer controlled gate length
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Application No.: US16473592Application Date: 2017-03-31
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Publication No.: US11296087B2Publication Date: 2022-04-05
- Inventor: Abhishek A. Sharma , Van H. Le , Gilbert Dewey , Shriram Shivaraman , Yih Wang , Tahir Ghani , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/025593 WO 20170331
- International Announcement: WO2018/182738 WO 20181004
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/49 ; H01L27/108 ; H01L29/45 ; H01L29/51 ; H01L29/66 ; H01L29/786

Abstract:
Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200152635A1 THIN FILM TRANSISTORS WITH SPACER CONTROLLED GATE LENGTH Public/Granted day:2020-05-14
Information query
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