Invention Grant
- Patent Title: Multichip package link error detection
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Application No.: US16938842Application Date: 2020-07-24
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Publication No.: US11307928B2Publication Date: 2022-04-19
- Inventor: Venkatraman Iyer , Robert G. Blankenship , Mahesh Wagh , Zuoguo Wu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; H04L9/40 ; H04L1/00 ; H04L1/20 ; G06F13/16 ; H04L1/16

Abstract:
First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
Information query