Invention Grant
- Patent Title: Stacked transistor structures with asymmetrical terminal interconnects
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Application No.: US16832500Application Date: 2020-03-27
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Publication No.: US11342227B2Publication Date: 2022-05-24
- Inventor: Aaron Lilak , Ehren Mannebach , Nafees Kabir , Patrick Morrow , Gilbert Dewey , Willy Rachmady , Anh Phan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L21/311 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L27/088 ; H01L29/04 ; H01L29/16

Abstract:
One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.
Public/Granted literature
- US20210305098A1 STACKED TRANSISTOR STRUCTURES WITH ASYMMETRICAL TERMINAL INTERCONNECTS Public/Granted day:2021-09-30
Information query
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