Invention Grant
- Patent Title: Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC
-
Application No.: US16585104Application Date: 2019-09-27
-
Publication No.: US11360846B2Publication Date: 2022-06-14
- Inventor: Gabriele Boschi , Roger May , Gabriele Paoloni , Nabajit Deka , Matteo Salardi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/20
- IPC: G06F11/20 ; G06F11/07 ; G06F11/18 ; G06F11/16

Abstract:
Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.
Public/Granted literature
- US20200026598A1 TWO DIE SYSTEM ON CHIP (SOC) FOR PROVIDING HARDWARE FAULT TOLERANCE (HFT) FOR A PAIRED SOC Public/Granted day:2020-01-23
Information query