公开(公告)号：US11360846B2

公开(公告)日：2022-06-14

申请号：US16585104

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Gabriele Boschi ,  Roger May ,  Gabriele Paoloni ,  Nabajit Deka ,  Matteo Salardi

IPC: G06F11/20 ,  G06F11/07 ,  G06F11/18 ,  G06F11/16

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

公开(公告)号：US11841776B2

公开(公告)日：2023-12-12

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G06F11/00 ,  G06F11/16 ,  G05B9/02 ,  G06F11/30 ,  G06F13/12 ,  G06F11/07

CPC classification number: G06F11/1641 ,  G05B9/02 ,  G06F11/0796 ,  G06F11/3055 ,  G06F13/122

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

公开(公告)号：US20190294125A1

公开(公告)日：2019-09-26

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G05B9/02 ,  G06F13/12 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.