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公开(公告)号：US20200241987A1
公开(公告)日：2020-07-30
申请号：US16830325
申请日：2020-03-26
Applicant: Intel Corporation
Inventor： Maurizio Iacaruso , Gabriele Paoloni
Abstract: A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.
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公开(公告)号：US11360870B2
公开(公告)日：2022-06-14
申请号：US16830325
申请日：2020-03-26
Applicant: Intel Corporation
Inventor： Maurizio Iacaruso , Gabriele Paoloni
Abstract: A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.
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3.发明授权公开(公告)号：US11360846B2
公开(公告)日：2022-06-14
申请号：US16585104
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Gabriele Boschi , Roger May , Gabriele Paoloni , Nabajit Deka , Matteo Salardi
Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.
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