Invention Grant
- Patent Title: Tri-gate architecture multi-nanowire confined transistor
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Application No.: US16147275Application Date: 2018-09-28
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Publication No.: US11387329B2Publication Date: 2022-07-12
- Inventor: Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta , Paul Fischer , Walid Hafez
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L29/51 ; H01L27/088 ; H01L29/778

Abstract:
Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.
Information query
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