Invention Grant
- Patent Title: Magnetoelectric spin orbit logic based minority gate
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Application No.: US16130905Application Date: 2018-09-13
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Publication No.: US11387404B2Publication Date: 2022-07-12
- Inventor: Huichu Liu , Tanay Karnik , Sasikanth Manipatruni , Daniel Morris , Kaushik Vaidyanathan , Ian Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L43/02 ; H01L43/10 ; H01L43/06 ; G11C11/16 ; G11C11/18
Abstract:
An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.
Public/Granted literature
- US20200091407A1 MAGNETOELECTRIC SPIN ORBIT LOGIC BASED MINORITY GATE Public/Granted day:2020-03-19
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