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    Combinatorial magneto electric spin orbit logic
    1.
    发明授权
    Combinatorial magneto electric spin orbit logic 有权

    公开(公告)号：US10749104B2

    公开(公告)日：2020-08-18

    申请号：US16217807

    申请日：2018-12-12

    Applicant: Intel Corporation

    Inventor： Huichu Liu ,  Daniel Morris ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Kaushik Vaidyanathan ,  Ian Young

    IPC: H01L43/02 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

    Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

    PATTERN MATCHING CIRCUIT
    2.
    发明申请
    PATTERN MATCHING CIRCUIT 审中-公开

    公开(公告)号：US20170286420A1

    公开(公告)日：2017-10-05

    申请号：US15085816

    申请日：2016-03-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Kaushik Vaidyanathan ,  Ram K. Krishnamurthy

    IPC: G06F17/30 ,  G06F21/56

    CPC classification number: G06F16/9014 ,  Y02D10/45

    Abstract: Embodiments include a pattern matching circuit that implements a Bloom filter including one or more hash functions. The hash functions may generate respective addresses corresponding to bits of a memory array. Various techniques for improving the area and/or power efficiency of the pattern matching circuit are disclosed. For example, a number of logic 1 bits per column of hash matrixes associated with the one or more hash functions may be restricted to a pre-defined number. A plurality of addresses generated by the hash functions may use the same column address to correspond to bits of a same column. A single read port memory may be used to simultaneously read two bits and generate an output signal that indicates whether the two bits are both a first logic value. Other embodiments may be described and claimed.

    System, Apparatus And Method For Simultaneous Read And Precharge Of A Memory
    6.
    发明申请
    System, Apparatus And Method For Simultaneous Read And Precharge Of A Memory 审中-公开

    公开(公告)号：US20190355411A1

    公开(公告)日：2019-11-21

    申请号：US15980813

    申请日：2018-05-16

    Applicant: Intel Corporation

    Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

    IPC: G11C11/4094 ,  G11C11/4091 ,  G11C11/4093 ,  G06F13/16

    Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

    Save-restore circuitry with metal-ferroelectric-metal devices
    10.
    发明授权
    Save-restore circuitry with metal-ferroelectric-metal devices 有权

    公开(公告)号：US10777250B2

    公开(公告)日：2020-09-15

    申请号：US16144896

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

    IPC: G11C11/22 ,  G06F1/3234 ,  G11C11/413 ,  G11C14/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

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