Invention Grant
- Patent Title: Techniques for preventing voltage tampering of security control circuits
-
Application No.: US16222564Application Date: 2018-12-17
-
Publication No.: US11443073B2Publication Date: 2022-09-13
- Inventor: Wei Yee Koay , Ting Lu , Ching Kooi Hor , Chin Ghee Ch'ng
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: IventIQ Legal LLP
- Agent Steven J. Cahill
- Main IPC: G06F1/08
- IPC: G06F1/08 ; H03K5/24 ; H03K3/03 ; H03K19/17768 ; G06F21/76

Abstract:
An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.
Public/Granted literature
- US20190138754A1 Techniques For Preventing Voltage Tampering Of Security Control Circuits Public/Granted day:2019-05-09
Information query