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公开(公告)号：US20220255757A1
公开(公告)日：2022-08-11
申请号：US17732852
申请日：2022-04-29
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US11323268B2
公开(公告)日：2022-05-03
申请号：US16456368
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US11281383B2
公开(公告)日：2022-03-22
申请号：US15940799
申请日：2018-03-29
Applicant: Intel Corporation
Inventor： Ting Lu , Sean R. Atsatt , Andrew Martyn Draper , Eric Michael Innis
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F3/06 , G06F21/79 , G06F12/16 , G11C17/18 , G06F21/60 , G06F21/76 , G06F21/85 , G06F21/75
Abstract: The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the encryption key, the configuration bitstream) stored in nonvolatile memory via side-channel attacks. A processor may generate a randomized fuse list and the fuses may be blown in the randomized order. Additionally or alternatively, the processor may randomize the wait time between programming of each fuse. Further, the processor may generate a simplified fuse list including only fuses to be blown. The disclosed security systems and methods may be used individually or in combination to prevent determination of sensitive data, such as the encryption key, by monitoring, for example, power consumption in side-channel attacks.
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公开(公告)号：US20190319805A1
公开(公告)日：2019-10-17
申请号：US16456368
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US20190097818A1
公开(公告)日：2019-03-28
申请号：US15719039
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ting Lu , Robert Landon Pelt , James Ryan Kenny
Abstract: The present disclosure provides systems and methods for improving provision of secret data on programmable devices. An appliance receives physical unclonable function (PUF) data pertaining to an integrated circuit. Secret data is provided to the appliance from a secret vault. Public and private PUF keys are derived based upon the PUF data. Further, ephemeral public and private keys are derived by the appliance. The public and private PUF keys, along with the ephemeral public and private keys are used to establish a secure channel for programming the secret data on the programmable device.
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Patent Agency Ranking
公开(公告)号：US10223014B1
公开(公告)日：2019-03-05
申请号：US15719058
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Sean R. Atsatt , Andrew Draper , Ting Lu , Steve Tuyen Vu , Scott Weber
IPC: G06G7/38 , H03K19/173 , G06F3/06
Abstract: A system for maintaining reconfigurable partitions in an integrated device includes a first buffer having channels that store configuration data and a mask. The system also includes first decompression circuitry having a second buffer coupled to the first buffer that stores the configuration data and second decompression circuitry having a third buffer coupled to the first buffer that stores the mask. The system also includes partition maintenance circuitry that applies the mask to the configuration data after the first decompression circuitry has decompressed the configuration data and the second decompression circuitry has decompressed the mask.
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公开(公告)号：US12183412B2
公开(公告)日：2024-12-31
申请号：US17033526
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Andrew Martyn Draper , Ting Lu , Kenneth Chen , Wei Chun Lau
Abstract: An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.
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公开(公告)号：US12047514B2
公开(公告)日：2024-07-23
申请号：US17732852
申请日：2022-04-29
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
CPC classification number: H04L9/3247 , G06F7/725 , H04L9/0643 , H04L9/3066 , H04L9/3234 , H04L9/3236 , H04L9/3252
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US11329833B2
公开(公告)日：2022-05-10
申请号：US15719039
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ting Lu , Robert Landon Pelt , James Ryan Kenny
Abstract: The present disclosure provides systems and methods for improving provision of secret data on programmable devices. An appliance receives physical unclonable function (PUF) data pertaining to an integrated circuit. Secret data is provided to the appliance from a secret vault. Public and private PUF keys are derived based upon the PUF data. Further, ephemeral public and private keys are derived by the appliance. The public and private PUF keys, along with the ephemeral public and private keys are used to establish a secure channel for programming the secret data on the programmable device.
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公开(公告)号：US11443073B2
公开(公告)日：2022-09-13
申请号：US16222564
申请日：2018-12-17
Applicant: Intel Corporation
Inventor： Wei Yee Koay , Ting Lu , Ching Kooi Hor , Chin Ghee Ch'ng
IPC: G06F1/08 , H03K5/24 , H03K3/03 , H03K19/17768 , G06F21/76
Abstract: An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.
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