Invention Grant
- Patent Title: Phase interpolation based clock data recovery circuit and communication device including the same
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Application No.: US17469062Application Date: 2021-09-08
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Publication No.: US11456851B2Publication Date: 2022-09-27
- Inventor: Hanseok Kim , Hobin Song , Jaehyun Park
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2020-0183067 20201224
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H03L7/093 ; H03L7/08 ; H04L7/033

Abstract:
A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.
Public/Granted literature
- US20220209930A1 PHASE INTERPOLATION BASED CLOCK DATA RECOVERY CIRCUIT AND COMMUNICATION DEVICE INCLUDING THE SAME Public/Granted day:2022-06-30
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