公开(公告)号：US20250040206A1

公开(公告)日：2025-01-30

申请号：US18583500

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Jinchan Yun ,  Daihong Huh ,  Jaehyun Park

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device is described. The device includes lower and upper channel layers over an active region on a substrate. The device further includes a middle insulating structure disposed between the lower and the upper channels. The device includes gate structures surrounding the channel layers, lower and upper source/drain regions disposed on the active region on at least one side of the gate structures. Between the lower and upper source/drain regions is a barrier structure. The lower and upper source/drain regions may each fill a lower recess region or an upper recess region, respectively. These recess regions are defined by the respective channel layers, the gate structures, and by the barrier structure. The side surface slopes within the upper and the lower recess regions may vary and the side surface slopes of each of the recess regions may be different from each other.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.

公开(公告)号：US11700012B2

公开(公告)日：2023-07-11

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03 ,  H03M1/66 ,  H03M7/16

CPC classification number: H03M1/742 ,  H03M1/66 ,  H03M7/165 ,  H04B1/16

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US11689205B2

公开(公告)日：2023-06-27

申请号：US17503802

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsuk Jang ,  Hanseok Kim ,  Jaehyun Park ,  Hobin Song ,  Jongshin Shin ,  Youngjin Chung

IPC: H04L1/20 ,  H04L25/03 ,  H03L7/08 ,  H03L7/081 ,  H04L1/00

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H04L1/0033 ,  H04L1/0036 ,  H04L1/203 ,  H04L25/03019 ,  H04L25/03885

Abstract: An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

公开(公告)号：US20230141322A1

公开(公告)日：2023-05-11

申请号：US17985193

申请日：2022-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyun Lee ,  Sunggeun Kim ,  Hyeonju Lee ,  Seuk Son ,  Kangjik Kim ,  Jaehyun Park

IPC: H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099

CPC classification number: H03L7/0807 ,  H03L7/089 ,  H03L7/093 ,  H03L7/0998

Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

公开(公告)号：US11190053B2

公开(公告)日：2021-11-30

申请号：US16889214

申请日：2020-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbong Lee ,  Beomwoo Gu ,  Jaehyun Park ,  Sanghyuk Wi

IPC: H02J50/12 ,  H02M7/48 ,  H02P27/08 ,  H02J50/80

Abstract: A wireless power transmitter may include: a power factor correction (PFC) circuit configured to convert first alternating current (AC) power input from a power source into direct current (DC) power; an inverter configured to convert the DC power output from the PFC circuit into second AC power; a power transmission circuit configured to transmit wireless power, based on the second AC power output from the inverter; and at least one processor configured to identify at least one of a voltage or a current of the DC power output from the PFC circuit, and control an operation of the inverter based on the identified at least one of the voltage or the current.

公开(公告)号：US20190304973A1

公开(公告)日：2019-10-03

申请号：US16444683

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

公开(公告)号：US20250022944A1

公开(公告)日：2025-01-16

申请号：US18668358

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Minsu Seol ,  Minseok Yoo ,  Jaehyun Park ,  Kyungeun Byun

IPC: H01L29/76 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.

公开(公告)号：US20240321960A1

公开(公告)日：2024-09-26

申请号：US18613324

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinchan Yun ,  Sungil Park ,  Jaehyun Park ,  Dongkyu Lee ,  Kyuman Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes a substrate, a device isolation layer, first channels, first gate lines covering the first channel, extending in a second horizontal direction, and spaced apart from each other in the first horizontal direction, first source/drain areas arranged on both sides of each of the first channels in the first horizontal direction, a second channel arranged apart from the first gate line in the vertical direction over any one of the first gate lines, a second gate line, second source/drain areas, a third channel arranged apart from the second gate line in the vertical direction over the second gate line, a third gate line, third source/drain areas, and a first lower source/drain contact extending in the vertical direction and connected to each of the first source/drain area, the second source/drain area, and the third source/drain area.

公开(公告)号：US11996704B2

公开(公告)日：2024-05-28

申请号：US17523476

申请日：2021-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomwoo Gu ,  Jaehyun Park ,  Chongmin Lee ,  Bohwan Choi

IPC: H02J50/12 ,  H01F27/42

CPC classification number: H02J50/12 ,  H01F27/42 ,  H02J2310/22

Abstract: A wireless power receiver receiving power from a wireless power transmitter is provided. The receiver includes a resonance circuit, a rectifier circuit, and a driver circuit. The resonance circuit includes first and second coils and a first capacitor. The rectifier circuit includes first and second rectifier circuits. The first rectifier circuit includes first through fourth MOSFETs. Sources of the first and second MOSFETs are connected to ends of a resonator including the first coil and the first capacitor. Sources of the third and fourth MOSFETs are connected to ground. The driver circuit is connected to gates of the first through fourth MOSFETs, When the driver circuit switches off the first and second MOSFETs and switches on the third and fourth MOSFETs, as currents are induced in the resonator and the second coil, the resonance circuit receives the wireless power, and the current induced in the second coil is rectified by the second rectifier circuit.