Invention Grant
- Patent Title: Non-volatile memory module architecture to support memory error correction
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Application No.: US17210008Application Date: 2021-03-23
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Publication No.: US11461042B2Publication Date: 2022-10-04
- Inventor: George Pax , Jonathan Scott Parry
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F3/06 ; G06F12/02 ; G11C5/04 ; G11C7/22 ; G11C16/32 ; G06F11/10 ; G11C11/00 ; G11C5/14 ; G11C7/10 ; G11C8/00 ; G11C29/52 ; G11C29/04

Abstract:
Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.
Public/Granted literature
- US20210349658A1 NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR CORRECTION Public/Granted day:2021-11-11
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