公开(公告)号：US20180129450A1

公开(公告)日：2018-05-10

申请号：US15861374

申请日：2018-01-03

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Parry

IPC: G06F3/06 ,  G11C29/52 ,  G11C8/00 ,  G11C7/10 ,  G11C5/14 ,  G06F11/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C5/04 ,  G11C5/141 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C16/32 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2207/2245

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US20230134996A1

公开(公告)日：2023-05-04

申请号：US17958915

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G06F11/10 ,  G11C29/00 ,  G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US20210349658A1

公开(公告)日：2021-11-11

申请号：US17210008

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G06F11/10 ,  G11C29/00 ,  G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US10963184B2

公开(公告)日：2021-03-30

申请号：US16518541

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Scott Parry

IPC: G06F11/00 ,  G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G06F11/10 ,  G11C29/00 ,  G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52 ,  G11C29/04

Abstract: Techniques for a non-volatile memory module are provided. In an example, an apparatus can include a first memory device comprising a first type of memory media, a second memory device comprising a second type of memory media, and a controller. The controller can transfer data from the first memory device to the second memory device based at least in part on loss of system power to the apparatus while operating on power provided by a backup power source, restore the data from the second memory device to the first memory device based at least in part on the system power to the apparatus being re-established, identity chip failure of the second memory device, the chip failure based at least in part on restoring the data from the second memory device to the first memory device, and operate the apparatus based at least in part on the chip failure identified.

公开(公告)号：US11461042B2

公开(公告)日：2022-10-04

申请号：US17210008

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Scott Parry

IPC: G11C29/00 ,  G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G06F11/10 ,  G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52 ,  G11C29/04

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US10359970B2

公开(公告)日：2019-07-23

申请号：US16201576

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Parry

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G11C29/04

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US10162569B2

公开(公告)日：2018-12-25

申请号：US15861374

申请日：2018-01-03

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Parry

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G11C29/04

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US20170206036A1

公开(公告)日：2017-07-20

申请号：US15000812

申请日：2016-01-19

Applicant: Micron Technology Inc.

Inventor： George Pax ,  Jonathan Parry

IPC: G06F3/06 ,  G11C29/52 ,  G11C8/00 ,  G06F11/10 ,  G11C5/14 ,  G11C7/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C5/04 ,  G11C5/141 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C16/32 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2207/2245

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US10339075B2

公开(公告)日：2019-07-02

申请号：US15693027

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff ,  George Pax ,  Timothy Mowry Hollis

IPC: G06F12/00 ,  G06F13/16 ,  G06F1/10 ,  G06F13/40 ,  G06F13/42

Abstract: A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.

公开(公告)号：US20190095131A1

公开(公告)日：2019-03-28

申请号：US16201576

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： George Pax ,  Jonathan Parry

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C5/04 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C16/32 ,  G11C29/52

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C5/04 ,  G11C5/141 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/005 ,  G11C16/32 ,  G11C29/52 ,  G11C29/883 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/2245

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.