Invention Grant
- Patent Title: Low resistance interconnect structure for semiconductor device
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Application No.: US16940034Application Date: 2020-07-27
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Publication No.: US11476191B2Publication Date: 2022-10-18
- Inventor: Jason Huang , Liang-Chor Chung , Cheng-Yuan Li
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L21/02 ; H01L21/285

Abstract:
The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.
Public/Granted literature
- US20210193565A1 LOW RESISTANCE INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE Public/Granted day:2021-06-24
Information query
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