公开(公告)号：US11749328B2

公开(公告)日：2023-09-05

申请号：US17871983

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US12069965B2

公开(公告)日：2024-08-20

申请号：US18353569

申请日：2023-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

公开(公告)号：US11778923B2

公开(公告)日：2023-10-03

申请号：US17525927

申请日：2021-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H01L43/10 ,  H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

公开(公告)号：US20220352043A1

公开(公告)日：2022-11-03

申请号：US17866807

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Liang-Chor Chung

IPC: H01L21/66 ,  H01L21/768

Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

公开(公告)号：US11476191B2

公开(公告)日：2022-10-18

申请号：US16940034

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jason Huang ,  Liang-Chor Chung ,  Cheng-Yuan Li

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285

Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.

公开(公告)号：US11177430B2

公开(公告)日：2021-11-16

申请号：US16443772

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.

公开(公告)号：US12283532B2

公开(公告)日：2025-04-22

申请号：US17866807

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Liang-Chor Chung

IPC: H01L21/66 ,  H01L21/768

Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

公开(公告)号：US12199036B2

公开(公告)日：2025-01-14

申请号：US17871532

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jason Huang ,  Liang-Chor Chung ,  Cheng-Yuan Li

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.

公开(公告)号：US11410714B2

公开(公告)日：2022-08-09

申请号：US16572329

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: G11C11/16 ,  H01L27/02 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

公开(公告)号：US20210193565A1

公开(公告)日：2021-06-24

申请号：US16940034

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jason Huang ,  Liang-Chor Chung ,  Cheng-Yuan Li

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02

Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.