Invention Grant
- Patent Title: Semiconductor device and method of forming embedded wafer level chip scale packages
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Application No.: US16918281Application Date: 2020-07-01
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Publication No.: US11488933B2Publication Date: 2022-11-01
- Inventor: Yaojian Lin , Pandi C. Marimuthu , Il Kwon Shim , Byung Joon Han
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L21/786 ; H01L21/784 ; H01L21/782 ; H01L21/82 ; H01L21/78

Abstract:
A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.
Public/Granted literature
- US20200335478A1 Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages Public/Granted day:2020-10-22
Information query
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