Invention Grant
- Patent Title: Hybrid scheme for improved performance for P-type and N-type FinFETs
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Application No.: US17120637Application Date: 2020-12-14
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Publication No.: US11495598B2Publication Date: 2022-11-08
- Inventor: Kuo-Cheng Chiang , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L29/04 ; H01L29/165 ; H01L29/78 ; H01L21/308 ; H01L21/84 ; H01L21/762 ; H01L21/02 ; H01L21/306 ; H01L21/311 ; H01L21/8238

Abstract:
A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.
Public/Granted literature
- US20210098459A1 Hybrid Scheme for Improved Performance for P-type and N-type FinFETs Public/Granted day:2021-04-01
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