Invention Grant
- Patent Title: Gate etch back with reduced loading effect
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Application No.: US17207425Application Date: 2021-03-19
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Publication No.: US11522065B2Publication Date: 2022-12-06
- Inventor: Yi-Chen Lo , Jung-Hao Chang , Li-Te Lin , Pinyen Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L29/66 ; H01L29/78 ; H01L29/423 ; H01L29/49 ; H01L29/165 ; H01L27/12 ; H01L27/088 ; H01L21/3065 ; H01L21/02 ; H01L21/28 ; H01L21/67 ; H01J37/00 ; H01L21/8234 ; H01L21/311 ; H01L21/3213 ; H01L21/84
Abstract:
A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
Public/Granted literature
- US20210210614A1 GATE ETCH BACK WITH REDUCED LOADING EFFECT Public/Granted day:2021-07-08
Information query
IPC分类:
