Invention Grant
- Patent Title: Package containing device dies and interconnect die and redistribution lines
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Application No.: US17121353Application Date: 2020-12-14
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Publication No.: US11532585B2Publication Date: 2022-12-20
- Inventor: Kuo-Chiang Ting , Chi-Hsi Wu , Shang-Yun Hou , Tu-Hao Yu , Chia-Hao Hsu , Ting-Yu Yeh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/56 ; H01L21/683 ; H01L21/48 ; H01L23/498 ; H01L23/538 ; H01L25/18 ; H01L25/00 ; H01L23/31

Abstract:
A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
Public/Granted literature
- US20210098408A1 Interconnect Chips Public/Granted day:2021-04-01
Information query
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