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公开(公告)号：US20250105185A1
公开(公告)日：2025-03-27
申请号：US18402944
申请日：2024-01-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuo-Chiang Ting , Sung-Feng Yeh , Ta Hao Sung , Gao-Long Wu , Shin-Jiun Fu
IPC: H01L23/00 , H01L23/498 , H01L23/522 , H01L25/00 , H01L25/065 , H01L25/18
Abstract: A method includes forming a function circuit on a semiconductor substrate of a device die, wherein the function circuit is in a functional circuit zone of the device die, forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device zone of the device die, forming a first plurality of bond pads in the functional circuit zone and at a surface of the device die, wherein the first plurality of bond pads have a first pattern density; and forming a second plurality of bond pads in the passive device zone and at the surface of the device die. The second plurality of bond pads have a second pattern density lower than the first pattern density.
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2.发明公开公开(公告)号：US20240222339A1
公开(公告)日：2024-07-04
申请号：US18152665
申请日：2023-01-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuo-Chiang Ting , Sung-Feng Yeh , Ta Hao Sung
CPC classification number: H01L25/105 , H01L21/568 , H01L23/3121 , H01L23/3135 , H01L24/05 , H01L24/08 , H01L24/19 , H01L24/20 , H01L24/80 , H01L24/95 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/13 , H01L2224/05647 , H01L2224/08237 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/19 , H01L2224/214 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/95001 , H01L2225/1023 , H01L2225/1058
Abstract: In an embodiment, a device includes a first integrated circuit die, wherein the first integrated circuit die includes a substrate formed of a semiconductor material and a conductive via penetrating through the substrate; a second integrated circuit die disposed laterally adjacent to the first integrated circuit die; a first gap-filling layer disposed between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer is formed of a material selected from silicon, silicon carbide, silicon oxynitride, silicon nitride, the semiconductor material of the substrate, or a combination thereof; and a third integrated circuit die attached to the first integrated circuit die in a face-to-back manner.
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公开(公告)号：US11996371B2
公开(公告)日：2024-05-28
申请号：US17339745
申请日：2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shang-Yun Hou , Weiming Chris Chen , Kuo-Chiang Ting , Hsien-Pin Hu , Wen-Chih Chiou , Chen-Hua Yu
IPC: H01L21/56 , H01L21/48 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L25/0655 , H01L25/50 , H01L2221/6835 , H01L2224/16227 , H01L2924/3511 , H01L2924/35121
Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
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公开(公告)号：US11852868B2
公开(公告)日：2023-12-26
申请号：US17873779
申请日：2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
CPC classification number: G02B6/1225 , G02B6/12019 , G02B2006/1213
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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公开(公告)号：US20220359231A1
公开(公告)日：2022-11-10
申请号：US17815434
申请日：2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih Ting Lin , Szu-Wei Lu , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu , Weiming Chris Chen
IPC: H01L21/56 , H01L21/768 , H01L21/48 , H01L23/538
Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
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Patent Agency Ranking
公开(公告)号：US11493689B2
公开(公告)日：2022-11-08
申请号：US16930558
申请日：2020-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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公开(公告)号：US11454773B2
公开(公告)日：2022-09-27
申请号：US17121060
申请日：2020-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Sung-Hui Huang , Kuan-Yu Huang , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
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公开(公告)号：US20220099887A1
公开(公告)日：2022-03-31
申请号：US17340363
申请日：2021-06-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Jiun Yi Wu , Hung-Yi Kuo , Shang-Yun Hou
Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.
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公开(公告)号：US12253729B2
公开(公告)日：2025-03-18
申请号：US17952681
申请日：2022-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Sung-Hui Huang , Kuan-Yu Huang , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
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公开(公告)号：US12242108B2
公开(公告)日：2025-03-04
申请号：US18526706
申请日：2023-12-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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