公开(公告)号：US11929340B2

公开(公告)日：2024-03-12

申请号：US17394213

申请日：2021-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yu Yeh ,  Chun-Hua Chang ,  Fong-Yuan Chang ,  Jyh Chwen Frank Lee

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L21/568 ,  H01L24/13 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/221

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

公开(公告)号：US20240178177A1

公开(公告)日：2024-05-30

申请号：US18428934

申请日：2024-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yu Yeh ,  Chun-Hua Chang ,  Fong-Yuan Chang ,  Jyh Chwen Frank Lee

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L21/568 ,  H01L24/13 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/221

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

公开(公告)号：US20210035884A1

公开(公告)日：2021-02-04

申请号：US16524172

申请日：2019-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yu Yeh ,  Cing-He Chen ,  Kuo-Chiang Ting ,  Weiming Chris Chen ,  Chia-Hao Hsu

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.

公开(公告)号：US11728238B2

公开(公告)日：2023-08-15

申请号：US16524172

申请日：2019-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yu Yeh ,  Cing-He Chen ,  Kuo-Chiang Ting ,  Weiming Chris Chen ,  Chia-Hao Hsu

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/3735 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/367 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2924/3511

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.

公开(公告)号：US11532585B2

公开(公告)日：2022-12-20

申请号：US17121353

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20210098408A1

公开(公告)日：2021-04-01

申请号：US17121353

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20240258261A1

公开(公告)日：2024-08-01

申请号：US18629641

申请日：2024-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US11978714B2

公开(公告)日：2024-05-07

申请号：US18068064

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20230124804A1

公开(公告)日：2023-04-20

申请号：US18068064

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20220230981A1

公开(公告)日：2022-07-21

申请号：US17394213

申请日：2021-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yu Yeh ,  Chun-Hua Chang ,  Fong-Yuan Chang ,  Jyh Chwen Frank Lee

IPC: H01L23/00

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.