Invention Grant
- Patent Title: Digital phase-frequency detector with split control loops for low jitter and fast locking
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Application No.: US17125595Application Date: 2020-12-17
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Publication No.: US11533058B2Publication Date: 2022-12-20
- Inventor: Zhengzheng Wu , Chao Song , Karthik Nagarajan
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Chui-kiu Teresa Wong
- Main IPC: H03L7/085
- IPC: H03L7/085 ; H03L7/197 ; H03L7/099 ; H03K3/037 ; H03K5/00 ; H03K19/20 ; H03L7/093 ; H04M1/725

Abstract:
A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.
Public/Granted literature
- US20220200608A1 DIGITAL PHASE-FREQUENCY DETECTOR WITH SPLIT CONTROL LOOPS FOR LOW JITTER AND FAST LOCKING Public/Granted day:2022-06-23
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