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1.发明授权公开(公告)号：US11533058B2
公开(公告)日：2022-12-20
申请号：US17125595
申请日：2020-12-17
Applicant: QUALCOMM Incorporated
Inventor： Zhengzheng Wu , Chao Song , Karthik Nagarajan
Abstract: A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.
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公开(公告)号：US20190097640A1
公开(公告)日：2019-03-28
申请号：US15714372
申请日：2017-09-25
Applicant: QUALCOMM Incorporated
Inventor： Karthik Nagarajan , Chenling Huang , Debesh Bhatta
IPC: H03L7/093 , H03L7/089 , H03K5/1252 , H03K5/26
CPC classification number: H03L7/093 , H03K5/1252 , H03K5/26 , H03K2005/00013 , H03L7/07 , H03L7/087 , H03L7/0891 , H03L7/22 , H03L7/235
Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
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公开(公告)号：US11177819B1
公开(公告)日：2021-11-16
申请号：US17111208
申请日：2020-12-03
Applicant: QUALCOMM Incorporated
Inventor： Zhengzheng Wu , Chao Song , Karthik Nagarajan
Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
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公开(公告)号：US10979068B1
公开(公告)日：2021-04-13
申请号：US16577074
申请日：2019-09-20
Applicant: QUALCOMM INCORPORATED
Inventor： Yi-Hung Tseng , Karthik Nagarajan
Abstract: A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.
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公开(公告)号：US11004209B2
公开(公告)日：2021-05-11
申请号：US16158079
申请日：2018-10-11
Applicant: QUALCOMM Incorporated
Inventor： Ying Chen , Yang Zhou , Karthik Nagarajan , Ning Bi
Abstract: Techniques and systems are provided for tracking objects in one or more video frames. For example, a first set of one or more bounding regions are determined for a video frame based on a trained classification network applied to the video frame. The first set of one or more bounding regions are associated with one or more objects in the video frame. One or more blobs can be detected for the video frame. A blob includes pixels of at least a portion of an object in the video frame. A second set of one or more bounding regions are determined for the video frame that are associated with the one or more blobs. A final set of one or more bounding regions is determined for the video frame using the first set of one or more bounding regions and the second set of one or more bounding regions. Object tracking can then be performed for the video frame using the final set of one or more bounding regions.
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Patent Agency Ranking
公开(公告)号：US10958279B1
公开(公告)日：2021-03-23
申请号：US16563083
申请日：2019-09-06
Applicant: QUALCOMM Incorporated
Inventor： Debesh Bhatta , Kevin Jia-Nong Wang , Karthik Nagarajan , John Abcarius , Andrew Weil , Christian Venerus , Jeffrey Mark Hinrichs
Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.
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7.发明申请METHOD AND APPARATUS FOR CLOSED LOOP CONTROL OF SUPPLY AND/OR COMPARATOR COMMON MODE VOLTAGE IN A SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER 有权用于闭环控制供应和/或比较器的模拟电压的方法和装置在一个后续的近似寄存器模拟电压数字转换器公开(公告)号：US20140247170A1
公开(公告)日：2014-09-04
申请号：US13782335
申请日：2013-03-01
Applicant: QUALCOMM INCORPORATED
Inventor： Karthik Nagarajan , Dinesh J. Alladi
IPC: H03M1/12
CPC classification number: H03M1/0604 , G06F1/3296 , H03M1/00 , H03M1/46 , Y02D10/172
Abstract: A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.
Abstract translation: 用于控制逐次逼近寄存器模数转换器和比较器共模电压的电源电压的方法和装置。 该方法包括：测量逐次逼近寄存器转换时间; 将逐次逼近寄存器转换时间与期望的转换时间进行比较; 并且如果需要，执行供电和/或比较器共模电压中的至少一个的闭环调节。 该装置由共模电压和调节器校正模块组成。 共模电压和调节器校正模块包括相位频率检测器，电荷泵，并且可以包括跨导单元。
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公开(公告)号：US11626883B2
公开(公告)日：2023-04-11
申请号：US17449250
申请日：2021-09-28
Applicant: QUALCOMM Incorporated
Inventor： Zhengzheng Wu , Chao Song , Karthik Nagarajan
Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
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公开(公告)号：US10411718B2
公开(公告)日：2019-09-10
申请号：US15714372
申请日：2017-09-25
Applicant: QUALCOMM Incorporated
Inventor： Karthik Nagarajan , Chenling Huang , Debesh Bhatta
IPC: H03L7/06 , H03L7/093 , H03L7/089 , H03K5/26 , H03K5/1252 , H03L7/07 , H03L7/087 , H03L7/22 , H03L7/23 , H03K5/00
Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
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10.发明授权Method and apparatus for closed loop control of supply and/or comparator common mode voltage in a successive approximation register analog to digital converter 有权用于逐次逼近寄存器模数转换器的电源和/或比较器共模电压的闭环控制的方法和装置公开(公告)号：US08994568B2
公开(公告)日：2015-03-31
申请号：US13782335
申请日：2013-03-01
Applicant: QUALCOMM Incorporated
Inventor： Karthik Nagarajan , Dinesh J Alladi
CPC classification number: H03M1/0604 , G06F1/3296 , H03M1/00 , H03M1/46 , Y02D10/172
Abstract: A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.
Abstract translation: 用于控制逐次逼近寄存器模数转换器和比较器共模电压的电源电压的方法和装置。 该方法包括：测量逐次逼近寄存器转换时间; 将逐次逼近寄存器转换时间与期望的转换时间进行比较; 并且如果需要，执行供电和/或比较器共模电压中的至少一个的闭环调节。 该装置由共模电压和调节器校正模块组成。 共模电压和调节器校正模块包括相位频率检测器，电荷泵，并且可以包括跨导单元。
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