Invention Grant
- Patent Title: Structure and formation method of chip package with conductive support elements to reduce warpage
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Application No.: US16452830Application Date: 2019-06-26
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Publication No.: US11600573B2Publication Date: 2023-03-07
- Inventor: Po-Hao Tsai , Techi Wong , Yi-Wen Wu , Po-Yao Chuang , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/56 ; H01L23/00 ; H01L23/31

Abstract:
A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.
Information query
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