Invention Grant
- Patent Title: Amplifier gain-tuning circuits and methods
-
Application No.: US17141726Application Date: 2021-01-05
-
Publication No.: US11616475B2Publication Date: 2023-03-28
- Inventor: Rong Jiang , Khushali Shah , Ravindranath D. Shrivastava , Parvez Daruwalla
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus & McFarland LLP
- Agent John Land, Esq.
- Main IPC: H03F1/26
- IPC: H03F1/26 ; H03F3/72 ; H03G1/00

Abstract:
Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
Public/Granted literature
- US20220216833A1 Amplifier Gain-Tuning Circuits and Methods Public/Granted day:2022-07-07
Information query