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公开(公告)号：US12101072B2
公开(公告)日：2024-09-24
申请号：US17933230
申请日：2022-09-19
Applicant: pSemi Corporation
Inventor： Ravindranath D. Shrivastava , Fleming Lam , Payman Shanjani
CPC classification number: H03H11/245 , H03H7/20
Abstract: Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.
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公开(公告)号：US12119814B2
公开(公告)日：2024-10-15
申请号：US18183806
申请日：2023-03-14
Applicant: pSemi Corporation
Inventor： Ravindranath D. Shrivastava , Alper Genc
IPC: H03K17/16 , H03K17/041 , H03K17/0412 , H03K17/06 , H03K17/687 , H03K17/693 , H04B1/44 , H01L27/06
CPC classification number: H03K17/687 , H03K17/063 , H01L27/0629
Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.
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公开(公告)号：US11616475B2
公开(公告)日：2023-03-28
申请号：US17141726
申请日：2021-01-05
Applicant: pSemi Corporation
Inventor： Rong Jiang , Khushali Shah , Ravindranath D. Shrivastava , Parvez Daruwalla
Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
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公开(公告)号：US11835978B1
公开(公告)日：2023-12-05
申请号：US17893677
申请日：2022-08-23
Applicant: pSemi Corporation
Inventor： Ravindranath D. Shrivastava , Payman Shanjani
Abstract: Methods and devices to reduce or remove slumps in power supplies are disclosed. The disclosed teachings can serve various applications, such as applications implementing RF switches. Using such teachings, an integrated method can benefit from two different modes of operation where either an external or an internal charge pump can be used to provide a desired negative voltage to various components within the integrated circuit. This can be done by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirement.
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公开(公告)号：US11777485B2
公开(公告)日：2023-10-03
申请号：US17660725
申请日：2022-04-26
Applicant: pSemi Corporation
Inventor： Ravindranath D. Shrivastava , Simon Willard , Peter Bacon
IPC: H03K17/04 , H03K17/0412
CPC classification number: H03K17/04123
Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.
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Patent Agency Ranking
公开(公告)号：US20220216833A1
公开(公告)日：2022-07-07
申请号：US17141726
申请日：2021-01-05
Applicant: pSemi Corporation
Inventor： Rong Jiang , Khushali Shah , Ravindranath D. Shrivastava , Parvez Daruwalla
Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
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公开(公告)号：US12081210B2
公开(公告)日：2024-09-03
申请号：US18473742
申请日：2023-09-25
Applicant: pSemi Corporation
Inventor： Eric S. Shapiro , Ravindranath D. Shrivastava , Fleming Lam , Matt Allison
IPC: H03K17/687
CPC classification number: H03K17/6871
Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.
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公开(公告)号：US20230291360A1
公开(公告)日：2023-09-14
申请号：US18185140
申请日：2023-03-16
Applicant: pSemi Corporation
Inventor： Rong Jiang , Khushali Shah , Ravindranath D. Shrivastava , Parvez H. Daruwalla
CPC classification number: H03F1/26 , H03F3/72 , H03G1/0088 , H03F2200/372 , H03F2200/294 , H03F2203/7239
Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
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公开(公告)号：US11722162B1
公开(公告)日：2023-08-08
申请号：US17649717
申请日：2022-02-02
Applicant: pSemi Corporation
Inventor： Chengkai Luo , Payman Shanjani , Ravindranath D. Shrivastava
CPC classification number: H04B1/0466 , H01Q1/50 , H04B1/0458
Abstract: Fail-safe methods and devices to protect the receiver of a transceiver in the event of an antenna failure are disclosed. The described devices implement inductive and capacitive elements to replace switches and can be used in any communication system or electronic circuit where the protection of a portion of the device from higher power signals is required. The inductive elements can be implemented using already existing inductors that are constituents of the receiver matching network. Configurations with off-chip capacitive or inductive components are also possible.
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公开(公告)号：US11671135B2
公开(公告)日：2023-06-06
申请号：US17492199
申请日：2021-10-01
Applicant: pSemi Corporation
Inventor： Ravindranath D. Shrivastava , Fleming Lam , Payman Shanjani
CPC classification number: H04B1/40 , H03F3/245 , H03H11/28 , H03F2200/294 , H03F2200/451
Abstract: An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.
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