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公开(公告)号：US12095351B2
公开(公告)日：2024-09-17
申请号：US17555754
申请日：2021-12-20
CPC分类号： H02M1/088 , H02M1/0006 , H02M1/0009 , H02M1/0032 , H02M3/158
摘要： A switching power converter architecture that is efficient across its entire power range, regardless of load level, by partitioning the power devices into segments for optimal gate drive and providing a local variable-voltage driver for each power device segment. Power device segments may be selectively enabled or disabled based on the level of power to be delivered to a load. In addition, an adaptive gate drive scheme enables dynamic control of the RON and QG values for each power converter device so that the power devices may operate at the lowest RON value at or near maximum power levels for reduced conduction losses, at the lowest RON×QG product value at mid-level loads for peak efficiency, and at the lowest QG value at light loads for reduced switching losses.
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公开(公告)号：US12034406B2
公开(公告)日：2024-07-09
申请号：US18178236
申请日：2023-03-03
发明人： John Birkbeck
CPC分类号： H03D7/1441 , H03D7/1408 , H03D7/1483 , H04B1/40
摘要： Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.
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公开(公告)号：US12032889B2
公开(公告)日：2024-07-09
申请号：US17190336
申请日：2021-03-02
申请人： Synopsys, Inc.
发明人： Jong Beom Park
IPC分类号： G06F30/36 , G06F18/23213 , G06F30/373 , G06F30/39 , G06N7/00 , G06N20/10 , G06F119/06 , G06N20/00
CPC分类号： G06F30/36 , G06F30/373 , G06F30/39 , G05B2219/45028 , G06F18/23213 , G06F2119/06 , G06N7/00 , G06N20/00 , G06N20/10
摘要： Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.
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公开(公告)号：US12032040B2
公开(公告)日：2024-07-09
申请号：US17682896
申请日：2022-02-28
摘要： Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage VREF and a fuse voltage VFUSE, and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (VTH) than VREF. Since VREF may be about 0.1V, that turn-ON voltage may be as low as about 0.1V+VTH, and thus would be less than a VDD_MIN of about 1V.
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公开(公告)号：US11990874B2
公开(公告)日：2024-05-21
申请号：US17985495
申请日：2022-11-11
申请人： pSemi Corporation
发明人： Jaroslaw Adamski
CPC分类号： H03F3/211 , H03F1/0227 , H03F1/0244 , H03F1/0261 , H03F1/223 , H03F3/265 , H03F3/3008 , H03F3/3037 , H03F2200/451 , H03F2200/61
摘要： Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
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公开(公告)号：US11957057B2
公开(公告)日：2024-04-09
申请号：US17296942
申请日：2020-07-14
发明人： Huijun Kang , Tongmin Wang , Jianbo Li , Zhiqiang Cao , Zongning Chen , Enyu Guo , Yiping Lu , Jinchuan Jie , Yubo Zhang , Tingju Li
IPC分类号： H10N10/855 , C01G23/00 , H10N10/01
CPC分类号： H10N10/855 , C01G23/006 , H10N10/01 , C01P2002/54 , C01P2002/72 , C01P2004/03 , C01P2006/32 , C01P2006/40
摘要： A CaTiO3-based oxide thermoelectric material and a preparation method thereof are disclosed. The CaTiO3-based oxide thermoelectric material has a chemical formula of Ca1-xLaxTiO3, where 0
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公开(公告)号：US11923765B2
公开(公告)日：2024-03-05
申请号：US17560700
申请日：2021-12-23
申请人： pSemi Corporation
发明人： Gregory Szczeszynski
摘要： Circuits and methods for protecting a multi-level power converter using no more than two high-voltage FET switches while allowing all or most other power switches to be low-voltage FET switches. Some embodiments provide protective high-voltage top and bottom FETs designed to saturate before the remaining low-power FET switches saturate. Other embodiments may use only low-power FETs for the power switches but provide protective circuits configured to be in an always-ON (conducting) state when in normal power conversion operation, and to quickly switch to an OFF (non-conducting) state in the event of transients or a fault condition. Optionally, one or more of the protective circuits may be used in a controlled manner to limit or block current flow during certain types of fault conditions and/or to limit in-rush current during startup of a power converter.
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公开(公告)号：US11909316B2
公开(公告)日：2024-02-20
申请号：US17968440
申请日：2022-10-18
申请人： pSemi Corporation
CPC分类号： H02M3/158 , H02M1/32 , H02H7/1213
摘要： Circuits and methods for protecting the switches of charge pump-based power converters from damage if a VOUT short circuit event occurs and/or if VIN falls rapidly with respect to VX or VOUT. A general embodiment includes a VX Detection Block coupled to the core block of a power converter. The VX Detection Block is coupled to VX and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in VX during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a VIN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of VIN to the power converter. The VIN Detection Block is coupled to VIN, and to VX or VOUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
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公开(公告)号：US11894840B2
公开(公告)日：2024-02-06
申请号：US17711845
申请日：2022-04-01
申请人： pSemi Corporation
IPC分类号： H03K17/693 , H03K19/17736 , H03K19/0944 , G06F13/42 , G06F13/40
CPC分类号： H03K17/693 , H03K19/0944 , H03K19/17744 , G06F13/4068 , G06F13/4282
摘要： Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.
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公开(公告)号：US11888468B2
公开(公告)日：2024-01-30
申请号：US17190122
申请日：2021-03-02
申请人： pSemi Corporation
IPC分类号： H03K17/687 , H03K17/10 , H03K17/693 , H03K17/16 , H01H11/00 , H03K17/06
CPC分类号： H03K17/6871 , H01H11/00 , H03K17/102 , H03K17/161 , H03K17/693 , H03K2017/066 , Y10T29/49105
摘要： An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
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