A semiconductor manufacturing apparatus includes one or more process modules, a scheduler, and a transfer controller. A product wafer of a lot that is transferred from a load port to one of the one or more process modules is replenished such that a total number of wafers that are simultaneously processed in the one or more process modules becomes N. When an advance lot being processed and a post lot to be processed subsequent to the advance lot have a same processing condition, the scheduler creates the transfer plan to replenish with the product wafer of the post lot instead of a dummy wafer such that the transfer controller transfers the product wafer and the dummy wafer to the one or more process modules according to the created transfer plan.