Invention Grant
- Patent Title: Transistor structure and method with strain effect
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Application No.: US17403402Application Date: 2021-08-16
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Publication No.: US11621350B2Publication Date: 2023-04-04
- Inventor: Xusheng Wu , Youbo Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L21/311 ; H01L29/66 ; H01L29/40
Abstract:
A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.
Public/Granted literature
- US20210376149A1 Transistor Structure and Method With Strain Effect Public/Granted day:2021-12-02
Information query
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