公开(公告)号：US11621350B2

公开(公告)日：2023-04-04

申请号：US17403402

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.

公开(公告)号：US11302784B2

公开(公告)日：2022-04-12

申请号：US16746618

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20240312876A1

公开(公告)日：2024-09-19

申请号：US18671580

申请日：2024-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L21/764 ,  H01L21/768 ,  H01L23/498 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L23/4821 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/49833 ,  H01L23/49894 ,  H01L29/41775 ,  H01L29/4991 ,  H01L2221/1042

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US20220262708A1

公开(公告)日：2022-08-18

申请号：US17739826

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L21/764 ,  H01L21/768 ,  H01L23/498 ,  H01L29/417 ,  H01L29/49

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11855155B2

公开(公告)日：2023-12-26

申请号：US17658779

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L29/456 ,  H01L29/665

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20210376149A1

公开(公告)日：2021-12-02

申请号：US17403402

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.

公开(公告)号：US11996353B2

公开(公告)日：2024-05-28

申请号：US17739826

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L21/764 ,  H01L21/768 ,  H01L23/498 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L23/4821 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/49833 ,  H01L23/49894 ,  H01L29/41775 ,  H01L29/4991 ,  H01L2221/1042

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11328982B2

公开(公告)日：2022-05-10

申请号：US16817111

申请日：2020-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L23/498 ,  H01L21/768 ,  H01L21/764 ,  H01L29/417 ,  H01L29/49

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11094821B2

公开(公告)日：2021-08-17

申请号：US16573898

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.

公开(公告)号：US20210083112A1

公开(公告)日：2021-03-18

申请号：US16573898

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.